rev. 0.0 /feb. 99 1 overview the direct rambus? rimm? module is a general purpose high-performance memory subsystem suitable for use in a broad range of applications including computer memory, personal computers, workstations, and other applications where high bandwidth and low latency are required. the 128mb direct rambus rimm module consists of eight 128m direct rambus dram (direct rdram?) devices. these are extremely high-speed cmos drams organized as 8m words by 16 or 18 bits. the use of rambus signaling level (rsl) technology permits 600mhz or 800mhz transfer rates while using conventional system and board design technologies. direct rdram devices are capable of sustained data transfers at 1.25 ns per two bytes (10ns per sixteen bytes). the architecture of the direct rdram allows the highest sustained bandwidth for multiple, simultaneous randomly addressed memory transactions. the separate control and data buses with independent row and column control yield over 95% bus efficiency. the direct rdram's thirty-two banks support up to four simultaneous transactions. features 184-pin 1mm pin spacing card size: 133.35mm x 31.75mm x 1.27mm (5.25? x 1.25? x 0.050?) 128mb direct rdram storage each rdram has 32banks, for 256banks total on module gold plated contacts rdrams use chip scale package (csp) serial presence detect support operates from a 2.5 volt supply ( 5%) low power and powerdown self refresh modes separate row and column buses for higher efficiency key timing parameters/part numbers the following table lists the frequency and latency bins available from rimm modules. an optional -lp designator is used to indicate low power modules. form factor the direct rambus rimm modules are offered in a 184-pin 1mm pin pitch form factor suitable for desktop and other system applications. organization i/o freq. mhz t rac (row access time) ns part number 64m x 16 600 53 HYMR11664-653 64m x 16 800 45 hymr11664-845 64m x 16 800 40 hymr11664-840 64m x 18 600 53 hymr11864-653 64m x 18 800 45 hymr11864-845 64m x 18 800 40 hymr11864-840 direct rambus ? rimm ? module 128 mbytes (64m x 16/18) based on 8mx16/18
page 2 rev. 0.0/ feb. 99 preliminary hymr11664/11864 series pinouts and pin names pin pin name pin pin name pin pin name pin pin name a1 gnd b1 gnd a47 nc b47 nc a2 ldqa8 b2 ldqa7 a48 nc b48 nc a3 gnd b3 gnd a49 nc b49 nc a4 ldqa6 b4 ldqa5 a50 nc b50 nc a5 gnd b5 gnd a51 vref b51 vref a6 ldqa4 b6 ldqa3 a52 gnd b52 gnd a7 gnd b7 gnd a53 scl b53 sa0 a8 ldqa2 b8 ldqa1 a54 vdd b54 vdd a9 gn d b9 gnd a55 sda b55 sa1 a10 ldqa0 b10 lcfm a56 svdd b56 svdd a11 gnd b11 gnd a57 sw p b57 sa2 a12 lctmn b12 lcfmn a58 vdd b58 vdd a13 gnd b13 gnd a59 rsck b59 rcmd a14 lctm b14 nc a60 gnd b60 gnd a15 gnd b15 gnd a61 rdqb7 b61 rdqb8 a16 nc b16 lrow2 a62 gnd b62 gnd a17 gnd b17 gnd a63 rdqb5 b63 rdqb6 a18 lrow1 b18 lrow0 a64 gnd b64 gnd a19 gnd b19 gnd a65 rdqb3 b65 rdqb4 a20 lcol4 b20 lcol3 a66 gnd b66 gnd a21 gnd b21 gnd a67 rdqb1 b67 rdqb2 a22 lcol2 b22 lcol1 a68 gnd b68 gnd a23 gnd b23 gnd a69 rcol0 b69 rdqb0 a24 lcol0 b24 ldqb0 a70 gnd b70 gnd a25 gnd b25 gnd a71 rcol2 b71 rcol1 a26 ldqb1 b26 ldqb2 a72 gnd b72 gnd a27 gnd b27 gnd a73 rcol4 b73 rcol3 a28 ldqb3 b28 ldqb4 a74 gnd b74 gnd a29 gnd b29 gnd a75 rrow1 b75 rrow0 a30 ldqb5 b30 ldqb6 a76 gnd b76 gnd a31 gnd b31 gnd a77 nc b77 rrow2 a32 ldqb7 b32 ldqb8 a78 gnd b78 gnd a33 gnd b33 gnd a79 rctm b79 nc a34 ls c k b34 lcmd a80 gnd b80 gnd a35 vcmos b35 vcmos a81 rctmn b81 rcfmn a36 sout b36 sin a82 gnd b82 gnd a37 vcmos b37 vcmos a83 rdqa0 b83 rcfm a38 nc b38 nc a84 gnd b84 gnd a39 gnd b39 gnd a85 rdqa2 b85 rdqa1 a40 nc b40 nc a86 gnd b86 gnd a41 vdd b41 vdd a87 rdqa4 b87 rdqa3 a42 vdd b42 vdd a88 gnd b88 gnd a43 nc b43 nc a89 rdqa6 b89 rdqa5 a44 nc b44 nc a90 gnd b90 gnd a45 nc b45 nc a91 rdqa8 b91 rdqa7 a46 nc b46 nc a92 gnd b92 gnd
rev. 0.0/ feb. 99 page 3 hymr11664/11864 series preliminary pin definition signal pins i/o type description g nd a1, a3, a5, a7, a9, a11, a13, a15, a17, a19, a21, a23, a25, a27, a29, a31, a33, a39, a52, a60, a62, a64, a66, a68, a70, a72, a74, a76, a78, a80, a82, a84, a86, a88, a90, a92, b1, b3, b5, b7, b9, b11, b13, b15, b17, b19, b21, b23, b25, b27, b29, b31, b33, b39, b52, b60, b62, b64, b66, b68, b70, b72, b74, b76, b78, b80, b82, b84, b86, b88, b90, b92 ground reference for rdram core and interface. 72 pins. lcfm b10 i rsl clock from master. interface clock used for receiving rsl signals from the channel. positive polarity. lcfmn b12 i rsl clock from master. interface clock used for receiving rsl signals from the channel. negative polarity. lcmd b34 i v cmos serial command pin. pin used to read from and write to the control registers. also used for power management. lcol4.. lcol0 a20, b20, a22, b22, a24 i rsl column bus. 5-pin bus containing control and address information for column accesses. lctm a14 i rsl clock to master. interface clock used for transmitting rsl signals to the channel. positive polarity. lctmn a12 i rsl clock to master. interface clock used for transmitting rsl signals to the channel. negative polarity. ldqa8.. ldqa0 a2, b2, a4, b4, a6, b6, a8, b8, a10 i/o rsl data bus a. a 9-pin bus carrying a byte of read or write data between the channel and the rdram. ldqa8 is non-functional on x16 devices ldqb8.. ldqb0 b32, a32, b30, a30, b28, a28, b26, a26, b24 i/o rsl data bus b. a 9-bit bus carrying a byte of read or write data between the channel and the rdram. ldqb8 is non-functional on x16 devices. lrow2.. lrow0 b16, a18, b18 i rsl row bus. 3-pin bus containing control and address infor- mation for row accesses. lsck a34 i v cmos clock input. pin used to read from and write to the con- trol registers. nc a16, b14, a38, b38, a40, b40, a43, b43, a44, b44, a45, b45, a46, b46, a47, b47, a48, b48, a49, b49, a50, b50, a77, b79 these pins are not connected. these 24 pins are all reserved for future use. rcfm b83 i rsl clock from master. interface clock used for receiving rsl signals from the channel. positive polarity. rcfmn b81 i rsl clock from master. interface clock used for receiving rsl signals from the channel. negative polarity.
page 4 rev. 0.0/ feb. 99 preliminary hymr11664/11864 series rcmd b59 i v cmos serial command input. pin used to read from and write to the control registers. also used for power manage- ment. rcol4.. rcol0 a73, b73, a71, b71, a69 i rsl column bus. 5-pin bus containing control and address information for column accesses. rctm a79 i rsl clock to master. interface clock used for transmitting rsl signals to the channel. positive polarity. rctmn a81 i rsl clock to master. interface clock used for transmitting rsl signals to the channel. negative polarity. rdqa8.. rdqa0 a91, b91, a89, b89, a87, b87, a85, b85, a83 i/o rsl data bus a. a 9-pin bus carrying a byte of read or write data between the channel and the rdram. rdqa8 is non-functional on x16 devices. rdqb8.. rdqb0 b61, a61, b63, a63, b65, a65, b67, a67, b69 i/o rsl data bus b. a 9-bit bus carrying a byte of read or write data between the channel and the rdram. rdqb8 is non-functional on x16 devices. rrow2.. rrow0 b77, a75, b75 i rsl row bus. 3-pin bus containing control and address infor- mation for row accesses. rsck a59 i v cmos clock input. pin used to read from and write to the con- trol registers. sa0 b53 i sv dd serial presence detect address 0. sa1 b55 i sv dd serial presence detect address 1. sa 2 b57 i sv dd serial presence detect address 2. scl a53 i sv dd serial presence detect clock. sda a55 i/o sv dd serial presence detect data (open collector i/o). si n b36 i/o v cmos serial i/o. pin for reading from and writing to the control registers. attaches to sio0 of the first rdram on the module. sout a 3 6 i/o v cmos serial i/o. pin for reading from and writing to the control registers. attaches to sio1 of the last rdram on the module. sv dd a56, b56 spd v oltage. used for signals scl, sda, swe, sa0, sa1 and sa2. swp a57 i sv dd serial presence detect write protect (active high). when low, the spd can be written as well as read. v cmos a35, b35, a37, b37 cmos i/o v oltage. used for signals cmd, sck, sin, sout. v dd a41, a42, a54, a58, b41, b42, b54, b58 supply voltage for the rdram core and interface logic. v ref a51, b51 logic threshold reference voltage for rsl signals. signal pins i/o type description
rev. 0.0/ feb. 99 page 5 hymr11664/11864 series preliminary functional diagram d q a 8 d q a 7 d q a 6 d q a 5 d q a 4 d q a 3 d q a 2 d q a 1 d q a 0 c f m c f m n c t m c t m n r o w 2 r o w 1 r o w 0 c o l 4 c o l 3 c o l 2 c o l 1 c o l 0 d q b 0 d q b 1 d q b 2 d q b 3 d q b 4 d q b 5 d q b 6 d q b 7 d q b 8 sio 0 sio 1 sck cmd v ref direct rdram (128/144mb) r d q a 8 r d q a 7 r d q a 6 r d q a 5 r d q a 4 r d q a 3 r d q a 2 r d q a 1 r d q a 0 r c f m r c f m n r c t m r c t m n r r o w 2 r r o w 1 r r o w 0 r c o l 4 r c o l 3 r c o l 2 r c o l 1 r c o l 0 r d q b 0 r d q b 1 r d q b 2 r d q b 3 r d q b 4 r d q b 5 r d q b 6 r d q b 7 r d q b 8 l d q a 8 l d q a 7 l d q a 6 l d q a 5 l d q a 4 l d q a 3 l d q a 2 l d q a 1 l d q a 0 l c f m l c f m n l c t m l c t m n l r o w 2 l r o w 1 l r o w 0 l c o l 4 l c o l 3 l c o l 2 l c o l 1 l c o l 0 l d q b 0 l d q b 1 l d q b 2 l d q b 3 l d q b 4 l d q b 5 l d q b 6 l d q b 7 l d q b 8 u1 u2 u3 u 8 . . . s i n l s c k l c m d v r e f s o u t r s c k r c m d vdd g nd 2 per rdram scl sda a0 a1 scl sa0 sa1 sda serial presence detect note 1: rambus channel signals form a loop through the rimm module , with the exception of the sio chain. d q a 8 d q a 7 d q a 6 d q a 5 d q a 4 d q a 3 d q a 2 d q a 1 d q a 0 c f m c f m n c t m c t m n r o w 2 r o w 1 r o w 0 c o l 4 c o l 3 c o l 2 c o l 1 c o l 0 d q b 0 d q b 1 d q b 2 d q b 3 d q b 4 d q b 5 d q b 6 d q b 7 d q b 8 sio 0 sio 1 sck cmd v ref direct rdram (128/144mb) d q a 8 d q a 7 d q a 6 d q a 5 d q a 4 d q a 3 d q a 2 d q a 1 d q a 0 c f m c f m n c t m c t m n r o w 2 r o w 1 r o w 0 c o l 4 c o l 3 c o l 2 c o l 1 c o l 0 d q b 0 d q b 1 d q b 2 d q b 3 d q b 4 d q b 5 d q b 6 d q b 7 d q b 8 sio 0 sio 1 sck cmd v ref direct rdram (128/144mb) d q a 8 d q a 7 d q a 6 d q a 5 d q a 4 d q a 3 d q a 2 d q a 1 d q a 0 c f m c f m n c t m c t m n r o w 2 r o w 1 r o w 0 c o l 4 c o l 3 c o l 2 c o l 1 c o l 0 d q b 0 d q b 1 d q b 2 d q b 3 d q b 4 d q b 5 d q b 6 d q b 7 d q b 8 sio 0 sio 1 sck cmd v ref direct rdram (128/144mb) v ref g nd 1 p er 2 rdram s v cmos g nd 1 p er 2 rdram s a2 sa 2 wp swp u0 vcc s v dd 0.1 m f 0.1 m f 0.1 m f sv dd g nd 0.1 m f . . . plus one near connector 47k ohm
page 6 rev. 0.0/ feb. 99 preliminary hymr11664/11864 series absolute maximum ratings dc recommended electrical conditions ac electrical specifications symbol parameter min max unit v i,abs voltage applied to any rsl or cmos p in with respect to gnd - 0.3 v dd + 0.3 v v dd,abs voltage on vdd with respect to gnd - 0. 5 v dd + 1.0 v t store storage temperature - 50 1 00 c symbol parameter and conditions min max unit v dd supply voltage 2.50 - 0.13 2.50 + 0.13 v v cmos cmos i/o pin power supply - 2.5v controllers: - for 1.8v controllers: 2.5 - 0.13 1.8 - 0.1 2.5 + 0.25 1.8 + 0.2 v v v ref reference voltage 1.4 - 0.2 1.4 + 0.2 v v il rsl input low voltage v ref - 0.5 v ref - 0. 2 v v ih rsl input high voltage v ref + 0. 2 v ref + 0.5 v v il,cmos cmos input low voltage - 0.3 0.5v cmos - 0.25 v v ih,cmos cmos input high voltage 0.5v cmos + 0.25 v cmos + 0.3 v v ol,cmos cmos output low voltage @ i ol,cmos = 1ma 0.3 v v oh,cmos cmos output high voltage @ i oh,cmos = -0.25ma v cmos - 0.3 v i ref v ref current @ v ref,max - 40 40 m a i sck,cmd cmos input leakage current @ (0 v cmos v dd ) - 40 40 m a i sin,sout cmos input leakage current @ (0 v cmos v dd ) -10.0 10.0 m a symbol parameter and conditions min max unit z module impedance 25.2 30.8 ohms t pd propagation delay, all rsl signals - 1.2 ns d t pd propagation delay variation of rsl signals with respect to an average clock delay a -0.01 0.01 ns d t pd-cmos propagation delay variation of sck and cmd signals with respect to an average clock delay a -0.1 0.1 ns v a /v in attenuation limit 4.0 % v xf /v in forward crosstalk coefficient (300ps input risetime 20%-80%) 0.8 % v xb /v in backward crosstalk coefficient (300ps input risetime 20%-80%) 1 % a. average clock delay is defined as the average delay from finger to finger of all rsl clock nets (ctm, ctmn, cfm, and cfmn).
rev. 0.0/ feb. 99 page 7 hymr11664/11864 series preliminary i dd - v dd s upply current profile i cmos - v cmos supply current profile i dd rimm module power test conditions -600 max -800 max unit i dd1 all rdrams in powerdown, self-refresh mode tbd/tbd a ma i dd2 all rdrams in nap mode t bd ma i dd3 all rdrams in standby mode, no commands tbd tbd ma i dd4 all rdrams in active mode, no commands tbd tbd ma i dd5 all rdrams running refresh cycles, with t rc = t rc,min tbd tbd ma i dd6 all rdrams running refresh cycles, with t rc = t ref /# of rows tbd tbd ma i dd7 one rdram cycling t rc = min, 1 bank, no col packets, remainder of rdrams in standby tbd tbd ma i dd8 one rdram cycling t rc = min, 1 bank, two dualocts per activate (32-byte transfers), remainder of rdrams in standby tbd tbd ma i dd9 one rdram burst read/write, 1 bank open, full bandwidth, col address changing every dualoct, remainder of rdrams in standby tbd tbd ma a. for modules with a -lp designator. i cmos rimm module power test conditions max unit i cmos1 current when rdrams are in powerdown, self-refresh state tbd ma i cmos2 current when cmos pins are used for register read/write operations (f=1mhz) tbd ma i cmos3 current when cmos pins are used for power management operations (f=100mhz) tbd ma
page 8 rev. 0.0/ feb. 99 preliminary hymr11664/11864 series t iming parameters the following timing parameters are from the rdrams pins, not the rimm. please refer to the rdram datasheet for detailed timing diagrams. parameter description min -40 -800 min -45 -800 min -53 -600 max units t rc row cycle time of rdram banks -the interval between rowa packets with act commands to the same bank. 28 28 28 - t cycle t ras ras-asserted time of rdram bank - the interval between rowa packet with act command and next rowr packet with prer a com- mand to the same bank. 20 20 20 60 m s b t cycle t rp row precharge time of rdram banks - the interval between rowr packet with prer a command and next rowa packet with act com- mand to the same bank. 8 8 8 - t cycle t pp precharge-to-precharge time of rdram device - the interval between successive rowr packets with prer a commands to any banks of the same device. 8 8 8 - t cycle t rr ras-to-ras time of rdram device - the interval between successive rowa packets with act commands to any banks of the same device. 8 8 8 - t cycle t rcd ras-to-cas delay - the interval from rowa packet with act com- mand to colc packet with rd or wr command). note - the ras-to- cas delay seen by the rdram core (t rcd,core ) is equal to t rcd,core = 1 + t rcd because of differences in the row and column paths through the rdram interface. 7 9 7 - t cycle t cac cas access delay - the minimum interval from rd command to q read data. 8 8 8 12 t cycle t cwd cas write delay (interval from wr command to d write data. 6 6 6 6 t cycle t cc cas-to-cas time of rdram bank - the interval between successive colc commands). 4 4 4 - t cycle t packet length of rowa, rowr, colc, colm or colx packet. 4 4 4 4 t cycle t rtr interval from colc packet with wr command to colc packet which causes retire, and to colm packet with bytemask. 8 8 8 - t cycle t offp the interval (offset) from colc packet with rda command, or from colc packet with retire command (after wra automatic precharge), or from colx packet with prex command to the equivalent rowr packet with prer. 4 4 4 4 t cycle t rdp interval from last colc packet with rd command to rowr packet with prer. 4 4 4 - t cycle t rtp interval from last colc packet with automatic retire command to rowr packet with prer. 4 4 4 - t cycle a. or equivalent prec or prex command. b. this is a constraint imposed by the core, and is therefore in units of m s rather than t cycle .
rev. 0.0/ feb. 99 page 9 hymr11664/11864 series preliminary serial presence detect contents to be determined layout drawing the following defines the rimm module dimensions. all units are in millimeters with inches in brackets[ ], where appro- priate. the maximum height of the module is 31.75mm(1.25?).
page 10 rev. 0.0/ feb. 99 preliminary hymr11664/11864 series
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